1. Technical Field
The present invention relates to semiconductor contact structures and fabrication methods, and in particular to contact structures made by direct patterning of dielectric material or by image reversal patterning.
2. Description of the Related Art
Typical conventional integration schemes for forming electrical contacts for transistors in a semiconductor chip include depositing a nitride stop layer on top of finished front end of line (FEOL) devices (e.g., transistors). An oxide layer is deposited and planarized. Contact patterns are formed by lithography on either a regular resist or resist on antireflection coating (ARC) mask stacks or multiple layer mask stacks, such as a tri-layer mask stack, which need to be removed in later steps. Plasma etch processes are used to transfer the contact patterns into the oxide layer by opening the ARC layer, etching through the oxide layer, which typically has a different thickness on the top of gate and source/drain areas of the transistors, and then stopping on the nitride stopping layer. The nitride stopping layer is etched through—stopping on silicide layers on tops of gate and source/drain areas.
Current integration schemes and process flows for contact formation etch contact holes and stop on top of the gates and on the top of silicides in the source/drain area. The etching is performed in five steps. These include open ARC, etch oxide (stop on the nitride stop layer), etch the nitride stop layer, strip the resist and ARC and perform a post plasma etching treatment, e.g., Ar plasma sputtering step.
When device pitches shrink down to the sub-80 nm regime, there is no space to accommodate a nitride stop layer between two gates with spacers. Without a nitride stop layer, it is extremely challenging for oxide etching processes to stop on the top of the gate or on the top of source/drain areas without damaging the silicide. Because of the narrowing of pitch spaces between gates, self-aligned contact (SAC) integration schemes are being used to form contacts. The possibility of misalignment in the lithography steps can make the actual openings to the source/drain areas very small, e.g., in the regime of less than 15 nm. This shrinking of contact hole open area can cause severe aspect ratio dependent etching (ARDE) or the so called reactive ion etch (RIE) lag effect. In a case of normal RIE lag, smaller open holes etch slower than those which have larger openings. In some instances, etching can totally stop in very small holes, such as those having diameters less than 10 nm in diameter.
Because of the shrinking of silicide layer thicknesses, e.g., <10 nm for 32 nm nodes and beyond, plasma etching of either the oxide layer or the nitride stopping layer can either thin or damage the silicide layer. Both effects can significantly increase the contact resistances of silicides on the tops of gates and source/drain areas. Because of the shrinking of contact hole openings, a pre-barrier layer deposition clean process, usually a step of plasma etching with Ar sputtering, can sputter oxide from the oxide wall of the holes down to the bottoms of holes to cause an increase in contact resistance.